1. Field of the Invention
The present invention relates to a semiconductor memory device in which a dynamic RAM control device supplies a controls signal which control a dynamic RAM, and more particularly, to a semiconductor memory device in which a dynamic RAM control device controls a static RAM.
2. Description of the Background Art
A RAM (Random Access Memory) is an IC memory which is capable of designating a certain area of a memory and freely reading and writing data at the designated area. RAMs are divided into DRAMs (Dynamic RAM), SRAMs (Static RAM) and other RAMs according to their structures. Usually, a semiconductor memory device is fabricated incorporating a DRAM or an SRAM depending on a need. However, in some cases, an already completed semiconductor memory device needs be modified at a user's request or for some other reason. To explain this, a semiconductor memory device which is comprised of a memory IC and a logic IC which controls the memory IC is taken as an example. If the two ICs are to be fabricated independently of each other, a DRAM is a usual choice for the memory IC since use of a DRAM will reduce the overall size of the package. Let us assume here that an SRAM is to be used as the memory IC instead of a DRAM and both the logic IC and the memory IC are to be formed on the same semiconductor chip in order to further reduce the size of the package but without changing the structure of the logic IC (See FIGS. 16 to 18). Such a modification is sometimes demanded in the industry.
FIG 16 is a view showing a structure of the semiconductor memory device in which the memory IC is formed by a DRAM. As can be seen in FIG. 16, the logic IC 10 and the memory IC 11 are independently formed. In FIG. 16, an address signal and a control signal are supplied from the logic IC 10 to the memory IC 11, thereby transferring a data signal between the logic IC 10 and the memory IC 11.
In general, if a logic IC and a memory IC are to be formed on the same semiconductor substrate (i.e., if the two ICs are to be formed in "one chip"), an SRAM is used as the memory IC considering the efficiency of manufacturing processes. FIG. 17 is a view of a semiconductor memory device 100 in which a logic part 20 and a memory part 21 which uses an SRAM are formed on the same semiconductor substrate. In the structure of FIG. 17 as well, it is within the semiconductor memory device 100 that an address signal and a control signal are supplied from the logic part 20 to the memory part 21 and a data signal is consequently transferred between the logic part 20 and the memory part 21.
Thus, it the semiconductor memory device in which the logic IC 10 and the memory IC 11 which uses a DRAM are formed independently of each other is to be completed as one chip as shown in FIG. 16, the memory IC 11 has to be changed to an SRAM. However, since the logic IC 10 is designed on a premise that the memory IC 11 is a DRAM, it is necessary not only to change the memory IC 11 from a DRAM to an SRAM but also to accordingly change a RAM interface of the logic IC 10 in compliance with the change from a DRAM to an SRAM.
Here arises a problem associated with the change of the RAM interface of the logic IC 10, which is designed for a DRAM, to an interface for an SRAM. That is, there is a difference between a DRAM and an SRAM with respect to addressing. In the following, typical addressing methods for a DRAM and an SRAM will be described.
As mentioned earlier, in the case of a DRAM, a row address and a column address are serially transferred to reduce the number of address bus lines so that the size of the package will be suppressed. To discriminate a row address from a column address within the memory as shown in FIG. 16, a row address strobe signal (hereinafter "RAS signal") and a column address strobe signal (hereinafter "CAS signal") are used as control signals and transferred in parallel form. Other necessary control signals are a write enable signal (hereinafter "We signal") which instructs writing and reading of data and an output enable signal (hereinafter "OE signal") which decides a data output of which memory IC is to be selected when the memory IC shares the data line with other memory IC. The WE signal is usually at a low level when instructing writing of data and at a high level when instructing reading of data.
1. Read Cycle of DRAM PA0 2. Write Cycle of DRAM PA0 2-1. Early Write Cycle PA0 2-2. Delayed Write Cycle PA0 3. Read Cycle of SRAM PA0 4. Write Cycle of SRAM PA0 5. Means for Serially Supplying Addresses Using Multiplexer PA0 6. Other Means Serially Supplying Addresses
A read cycle of a DRAM will be described with reference to FIG. 18, which is a timing chart which shows a read cycle of a regular DRAM. In FIG. 18, the read cycle starts at a fall of the RAS signal. After a time d1 upon the fall of the RAS signal, the CAS signal completes falling. The time d1 is a minimum necessary interval between the low-level RAS signal and the low-level CAS signal. There is no possibility that the RAS signal will come after the CAS signal. A time d2 is a set up time for the row address signal. The row address signal is supplied the time d2 ahead of the RAS signal. In other words, the row address must be determined the time d2 ahead of the RAS signal. For a time d3 after the fall of the RAS signal, the row address signal must hold the same data.
On the other hand, the column address signal is supplied a time d4 ahead of the CAS signal. This means that the column address must be determined the time d4 ahead of the CAS signal. For a time d5 after the fall of the CAS signal, the column address signal must hold the same data.
It is necessary that the WE signal completes transition to the high level a time d6 ahead of the CAS signal. A time d7 is a time from the fall of the CAS signal to outputting of effective data. In general, d1+d7 is the access time of the DRAM.
As described above, during the read cycle, the RAS signal and the CAS signal latch the low address signal and the column address signal, respectively. After the time d7 from the latching, data stored at the addresses which are designed by the low address signal and the column address signal is outputted.
Now, a write cycle will be described. Since an early write cycle and a delayed write cycle are major write cycles, only these two typical write cycles will be described below.
FIG. 19 is a timing chart showing an early write cycle of a regular DRAM. The early write cycle is characterized in that the trailing edge of the WE signal comes earlier than the trailing edge of the CAS signal.
An early write cycle starts at a fall of the RAS signal. After a time d8 upon fall of the RAS signal, the CAS signal completes falling. The time is d8 a minimum necessary interval between the low-level RAS signal and the low-level CAS signal. There is no possibility that the RAS signal will come after the CAS signal.
A time d9 is a set up time for the row address signal. The row address signal is supplied the time d9 ahead of the RAS signal. In other words, the row address must be determined the time d9 ahead of the RAS signal. For a time d10 after the fall of the RAS signal, the row address signal must hold the same data.
On the other hand, the column address signal is supplied a time d11 ahead of the CAS signal. This means that the column address must be designated the time d11 ahead of the CAS signal. For a time d12 after the fall of the CAS signal, the column address signal must hold the same data.
It is necessary that WE signal completes transition to the low level a time d13 ahead of the CAS signal. With the WE signal fixed at the low level, inputting of effective data starts a time d14 ahead of the CAS signal. Inputting of the effective data continues for a time d15 after the fall of the CAS signal.
Thus, in the early write cycle, the RAS signal and the CAS signal latch the low address signal and the column address signal, respectively, to designate the address. The WE signal falls to the low level before the trailing edge of the CAS signal, and the trailing edge of the CAS signal which is supplied during the low-level period of the WE signal is used as a latch signal for data which is to be written.
FIG. 20 is a timing chart showing a delayed write cycle of a regular DRAM. A delayed write cycle is characterized in that the trailing edge of the CAS signal comes ahead of the trailing edge of the WE signal.
A delayed write starts at a fall of the RAS signal. After a time d16 upon fall of the RAS signal, the CAS signal completes falling. The time is d16 a minimum necessary interval between the low-level RAS signal and the low-level CAS signal. There is no possibility that the RAS signal will come after the CAS signal.
A time d17 is a set up time for the row address signal. The row address signal is supplied the time d17 ahead of the RAS signal. In other words, the row address must be designated the time d17 ahead of the RAS signal. For a time d18 after the fall of the RAS signal, the row address signal must hold the same data.
On the other head, the column address signal is supplied a time d19 ahead of the CAS signal. This means that the column address must be designated the time d19 ahead of the CAS signal. For a time d20 after the fall of the CAS signal, the column address signal must hold the same data.
A time between the fall of the WE signal to the rise of the next RAS signal is a hold time of the RAS signal, i.e., a time d21. A time between the fall of the WE signal to the rise of the next CAS signal is a hold time of the CAS signal, or a time d23.
A time between the fall of the CAS signal to the rise of the next WE signal is a hold time of a write instruction, i.e., a time d22.
A time between the fall of the WE signal to the rise of the next WE signal is a hold time of a write instruction, i.e., a time d24.
Inputting of effective data starts a time d25 ahead of the WE signal. For a time d26 upon the fall of the WE signal, inputting of the effective data must continue. A time from the fall of the WE signal to the next OE signal is a hold time of the output enable signal after writing, that is, a time d27.
Thus, during a delayed write cycle, although the addressing method for designating the row and the column addresses is the same as that for an early write cycle in that the RAS signal and the CAS signal are used to designate the addresses, one difference is that the trailing edge of the WE signal which comes behind the trailing edge of the CAS signal is used as a latch signal for data which is to be written.
Next, a read timing and a write timing in a regular synchronous SRAM will be described. FIG. 21 shows a read timing. In FIG. 21, an address signal is supplied a time d28 ahead of a fall of a chip enable signal (hereinafter "CE signal"). The address signal should remain effective for a time d29 after the fall of the CE signal. That is, the address signal is supplied during the time d28 and the time d29 as the CE signal falls. A time d30 is a delay time from latching of the address signal to outputting of a data signal.
Thus in a read cycle of the SRAM, the WE signal is always at the high level, the address signal is latched by a fall of the CE signal, and data held at the address which is designated by the address signal is outputted after a delay of the time d30.
FIG. 22 shows a write timing. In FIG. 22, an address signal is supplied a time d31 ahead of a fall of the CE signal. The address signal should remain effective for a time d32 after the fall of the CE signal. In other words, the address signal is supplied during the time d31 and the time d32 as the CE signal falls. The WE signal rises after the time d35 from the fall of the CE signal. A time d35 is a minimum necessary interval between the CE signal and the WE signal.
A data signal is inputted a time d33 ahead of a rise of the WE signal. The data signal must remain effective for a time d34 after the rise of the WE signal. In short, the data signal is supplied during the time d33 and the time d34 as the WE signal rises.
Thus, writing of data in the synchronous SRAM starts at a rise of the WE signal. The trailing edge of the CE signal comes prior to the rising edge of the WE signal, whereby desired data is written at a designated address.
As described above, an SRAM and a DRAM designated an address and latch data to be written in a different manner. A major difference between an SRAM and a DRAM to be particularly noted is that a row address and a column address are serially transferred in a DRAM.
To use a multiplexer is one of the options for supplying a row address and a column address in serial form. In the following, an address multiplexing method for a DRAM will be described with reference to FIGS. 23 and 24.
FIG. 23 is a block diagram showing a multiplexer 3 and a structure surrounding the same. In FIG. 23, the multiplexer 3 is connected to a signal generation circuit 1 which generates the RAS, the CAS and the WE signals, which are to be supplied to the DRAM, when a read, a write and a clock signals are respectively received, and to an RFSH signal which determines a refresh timing. The multiplexer 3 is also connected to an external system 2 which transmits the row address signal and the column address signal in parallel form. As herein termed, the external system 2 refers to a micro computer, a logic IC or etc.
From the external system 2, the row address signal and the column address signal are fed in parallel form to the multiplexer 3 where they are converted into serial form. The signal generation circuit 1 supplies an MPX signal which switches outputs of the multiplexer 3 as described later. Since the signal generation circuit 1 is not much relevant to an explanation of the address multiplexing method, the signal generation circuit 1 will not be described in detail with respect to its structure and other features.
The multiplexer 3 is a selector as far as its function is concerned. The multiplexer 3 is comprised of n switching circuits SC1 to SCn (N=1-8). The switching circuits SC1 to SCn each have two input terminals (1A,1B) . . . (nA,nB). Row address signals RAnm (n=1-8, m=1,2, . . . ) are fed to the input terminals 1A to nA from the external system 2 while column address signals CAnm (n=1-8; m=1, 2, . . . ) are fed to the input terminals 1B to nB. The switching circuits SC1 to SCn also respectively have output terminals 1Y and nY from which output signals SER1 to SERn are respectively outputted. Further, the switching circuits SC1 to SCn each have a selector switch S to receive the MPX signal from the signal generation circuit 1.
Basically, in the multiplexer 3, signals received at the input terminals 1B to nB are allowed to the output terminals 1Y to nY when a low level signal is received by the selector switches S. When a high level signal is fed to the selector switch S, signals received at the input terminals 1A to nA are allowed to the output terminals 1Y to nY.
FIG. 24 is a timing chart illustrating a case where parallel data transmitted from the external system 2 is converted into serial data by the multiplexer 3. In FIG. 24, when the MPX signal which is to be supplied to the selector switch S from the signal generation circuit 1 is at the low level, the row address signals RAnm (n=1-8, m=1, 2, . . . ) are inputted as the output signals SER1 to SERn. On the other hand, it the MPX signal which is at the high level, the column address signals CAnm (n=1-8, m=1, 2, . . . ) are outputted as the output signals SER1 to SERn. Thus, the MPX signal is switched alternately between the high level and the low level, whereby the row address and the column address signals are serially outputted.
Where a row address and a column address signals are converted into serial form by a multiplexer in this manner, it is possible to supply address signals in parallel form by simply removing the multiplexer, and therefore, it is possible to modify a RAM interface from a DRAM interface structure to an SRAM interface structure. However, some semiconductor memory devices do not comprise a multiplexer from the beginning.
FIG. 25 shows other means for serially supplying addresses without using a multiplexer. In FIG. 25, a counter circuit 40 is connected before a logic IC 50. The counter circuit 40 frequency-divides a clock signal once to three times into outputs Q1 to Q3. The outputs Q1 to Q3 are outputted through the logic IC 50 as the RAS and the CA signals. The counter circuit 40 also outputs and output Q4 from its inner flip-flop circuit as a serial address. The timing chart of FIG. 25 shows timings at which the row address and the column address of the output Q4 are latched by the RAS signal and the CAS signal.
In some other cases where a serial address is directly supplied from a micro computer to a DRAM, it is very difficult to convert address signals into parallel form.
As heretofore described, in a semiconductor memory device which is comprises of a memory IC and a logic IC which controls the memory IC, it is sometimes necessary to change the memory IC from a DRAM to an SRAM. It a row address signal and a column address signal are supplied in serial form using a multiplexer, the address signals can be supplied in parallel form instead of serial form by removing the multiplexer. In this case, however, not only removal of the multiplexer but also time-consuming verification of operations of the logic IC are necessary as well.
In addition, the inner structure of the logic IC must be modified to deal with a difference between a DRAM and an SRAM with respect to timings of control signals, which is not easy.